Cluster‐based approach for improving graphics processing unit performance by inter streaming multiprocessors locality. Issue 5 (1st September 2015)

• Record Type: Journal Article
• Authors: Keshtegar, Mohammad Mahdi; Falahati, Hajar; Hessabi, Shaahin
• Is Part Of: IET computers & digital techniques. Volume 9:Issue 5(2015)
• Page Start: 275
• Page End: 282
• Publication Date: 2015-09-01
• Subjects: graphics processing units -- pattern clustering -- multiprocessing systems -- multi‐threading -- cache storage -- power aware computing; cluster‐based approach -- graphics processing unit performance -- interstreaming multiprocessor locality -- general‐purpose computing -- high performance computing -- GPU -- multithreading -- private data cache -- single instruction multiple thread core -- SIMT core -- global memory -- public memory -- parallel processing -- off‐chip memory requests -- miss events -- on‐chip caches -- cluster‐based architecture -- SIMT cores -- energy consumption overhead; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2014.0092
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Owing to a new platform for high performance and general‐purpose computing, graphics processing unit (GPU) is one of the most promising candidates for faster improvement in peak processing speed, low latency and high performance. As GPUs employ multithreading to hide latency, there is a small private data cache in each single instruction multiple thread (SIMT) core. Hence, these cores communicate in many applications through the global memory. Access to this public memory takes long time and consumes large amount of power. Moreover, the memory bandwidth is limited which is quite challenging in parallel processing. The missed memory requests in last level cache that are followed by accesses to the slow off‐chip memory harm power and performance significantly. In this research, the authors introduce a light overhead mechanism to reduce off‐chip memory requests which are triggering by miss events in on‐chip caches. The authors propose a cluster‐based architecture to capture the similarity of memory requests between SIMT cores and provide data for missed requests by adjacent cores. Simulation results reveal that the proposed architecture enhances the geometric mean of instructions per cycle by 6.3% for evaluated benchmarks, whereas the maximum gain is 22%. Furthermore, the geometric mean of total energy consumption overhead is 4.8% for evaluated applications.