Built‐in self test design of power switch with clock‐gated charge/discharge transistor. Issue 2 (1st March 2014)

• Record Type: Journal Article
• Authors: Xin, Chen; Ning, Wu; Na, Bai; Hui, Huang; Wei, Hu
• Is Part Of: IET computers & digital techniques. Volume 8:Issue 2(2014)
• Page Start: 59
• Page End: 69
• Publication Date: 2014-03-01
• Subjects: built‐in self test -- fault trees -- low‐power electronics -- power semiconductor switches -- power transistors -- semiconductor device testing -- system‐on‐chip; built‐in self test design -- clock‐gated charge‐discharge transistor -- header power switches -- low‐power system‐on‐chip -- manufacturing defects -- footer power switches -- BIST circuit -- test clock -- test patterns -- test vector length -- fault‐free -- SMIC 1P6M logic process -- size 0.18 mum -- power 2.04 mW -- frequency 20 MHz; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2013.0081
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : It is becoming common to implement header (footer) power switches in low‐power system‐on‐chip. However, the switches are not tested for manufacturing defects in most designs currently. In this study, a novel built‐in self test (BIST) solution for power switch is proposed. To accelerate the test of the header (footer) switches, a charge (discharge) transistor is adopted in the proposed BIST circuit and the corresponding charge (discharge) transistor is gated by the test clock. Therefore the number of test patterns, the length of test vectors and the test time are all decreased. Besides, the test responses can be identified easily. If the test responses are all logic‐high, the tested switches are fault‐free. Or else, the tested switches are faulty. In addition, the structure of the proposed BIST circuit can be scaled freely with the amount of switches. For m switches, it takes m + 2 cycles to locate the faulty switches at worst. Finally, to verify the proposed BIST circuit, the BIST design with 255 header switches is implemented with SMIC 0.18 μm 1P6M logic process. The corresponding area is 0.043 mm 2 . The simulation results show that the BIST circuit can locate the possible manufacturing defects in the switches and discharge transistors within 257 clock cycles. The corresponding consumed power is 2.04 mW when the test frequency is 20 MHz.