Automatic management of Software Programmable Memories in Many‐core Architectures. Issue 6 (1st November 2016) - Shrivastava, Aviral; Dutt, Nikil; Cai, Jian; Shoushtari, Majid; Donyanavard, Bryan; Tajik, Hossein
Abstract : Software Programmable Memories, or SPMs, are raw on‐chip memories that are not implicitly managed by the processor hardware, but explicitly by software. For example, while caches fetch data from memories automatically and maintain coherence with other caches, SPMs explicitly manage data movement between memories and other SPMs through software instructions. SPMs make the design of on‐chip memories simpler, more scalable, and power efficient, but also place additional burden for programming of SPM‐based processors. Traditionally, SPMs have been utilised in embedded systems, especially multimedia and gaming systems, but recently research on SPM‐based systems has seen increased interest as a means to solve the memory scaling challenges of many‐core architectures. This study presents an overview of the state‐of‐the‐art in SPM management techniques in many‐core processors, summarises some recent research on SPM‐based systems, and outlines future research directions in this field.