Unified multi‐objective mapping and architecture customisation of networks‐on‐chip. Issue 6 (1st November 2013)

• Record Type: Journal Article
• Authors: Morgan, Ahmed A.; Elmiligi, Haytham; El‐Kharashi, Mohamed Watheq; Gebali, Fayez
• Is Part Of: IET computers & digital techniques. Volume 7:Issue 6(2013)
• Page Start: 282
• Page End: 293
• Publication Date: 2013-11-01
• Subjects: genetic algorithms -- integrated circuit design -- integrated circuit reliability -- network‐on‐chip -- network routing; unified multiobjective mapping customisation -- unified multiobjective architecture customisation -- networks‐on‐chip design -- NoC standard architectures -- architectural structure -- network performance maximization -- cost minimization -- multiobjective optimisation -- genetic algorithms -- power cost metric -- area cost metric -- delay performance metric -- reliability performance metric -- application traffic; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2013.0017
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : One of the challenging problems in networks‐on‐chip (NoC) design is optimising the architectural structure of the on‐chip network in order to maximise the network performance while minimising the corresponding costs. In this study, a methodology for multi‐objective optimisation of NoC standard architectures using Genetic Algorithms is presented. The methodology considers two cost metrics, power and area, and two performance metrics, delay and reliability. Our methodology combines the best selection of NoC standard topology, the optimum mapping of application cores onto that topology, and the best routing of application traffic traces over the generated network. The methodology is evaluated by applying it to different NoC benchmark applications as case studies. Results show that the architectures generated by our methodology outperform those of other standard architecture customisation techniques with respect to four metrics: power, area, delay and reliability, and their combination.