Globally asynchronous systems of interactive Moore state machines. Issue 4 (1st July 2016)

• Record Type: Journal Article
• Authors: Marakhovsky, Viacheslav Borisovich; Vadimovich Surkov, Alexey
• Is Part Of: IET computers & digital techniques. Volume 10:Issue 4(2016)
• Page Start: 186
• Page End: 192
• Publication Date: 2016-07-01
• Subjects: finite state machines -- parallel processing -- synchronisation -- timing circuits -- asynchronous circuits -- multiprocessor interconnection networks -- graph theory -- logic design -- clocks; interactive Moore state machines -- globally asynchronous systems -- parallel interacting blocks -- system blocks -- GALA design methodology -- globally asynchronous‐locally arbitrary design methodology -- synchronisation stratum -- distributed asynchronous clock network -- local synch‐signals -- self‐timed circuit -- processor stratum -- handshake protocol -- logic circuits -- parallel synchronisation -- arbitrary interconnection graphs -- wave synchronisation -- acyclic interconnection graph; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2015.0130
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : The problem of organising the temporal behaviour of globally asynchronous systems consisting of parallel interacting blocks is discussed. System blocks are represented by the Moore state machine model. The earlier suggested GALA (Globally Asynchronous, Locally Arbitrary) design methodology is used. This methodology is based on decomposing the system to a Processors Stratum (stratum of blocks) and a Synchronisation Stratum (synch‐stratum). The synch‐stratum acts as a distributed asynchronous clock network that produces local synch‐signals for the processor stratum, which basically can be a synchronous prototype. The synch‐stratum is a self‐timed circuit that interacts with the processor stratum (system devices) via the handshake protocol. Every local device that has received the request signal from the synch‐stratum produces the acknowledgment signal and sends it back. In this study, some logic circuits of universal modules are suggested. They provide an easy way to design any synch‐stratum for parallel synchronisation of system blocks with arbitrary interconnection graphs and for wave synchronisation of system blocks with acyclic interconnection graph.