Predicting future complementary metal–oxide–semiconductor technology – challenges and approaches. Issue 6 (1st November 2016)

• Record Type: Journal Article
• Authors: Aitken, Robert; Chandra, Vikas; Cline, Brian; Das, Shidhartha; Pietromonaco, David; Shifren, Lucian; Sinha, Saurabh; Yeric, Greg
• Is Part Of: IET computers & digital techniques. Volume 10:Issue 6(2016)
• Page Start: 315
• Page End: 322
• Publication Date: 2016-11-01
• Subjects: CMOS integrated circuits -- microprocessor chips -- integrated circuit design -- semiconductor device manufacture; complementary metal‐oxide‐semiconductor technology -- CPU architects -- design‐technology cooptimisation' -- DTCO -- microarchitecture; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2015.0210
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Long timescales and complex design processes require that CPU architects and microarchitects have early access to information about future manufacturing processes. In some cases, this means that future technology must be predicted in advance of it actually being developed. In addition, close collaboration with the foundries, known as 'Design‐Technology Co‐Optimisation', or DTCO, allows the mutual influence during development of microarchitecture, physical IP (standard cells and memories), and process technology. This predictive technology, in conjunction with early technology information or not, allow design exploration in the form of trial runs of synthesis, place and route to determine the predicted effects of various technology choices on CPU power, performance, and area.