Test data compression using hierarchical block merging technique. Issue 4 (31st May 2018)

• Record Type: Journal Article
• Authors: Vohra, Harpreet; Singh, Amardeep
• Is Part Of: IET computers & digital techniques. Volume 12:Issue 4(2018)
• Page Start: 176
• Page End: 185
• Publication Date: 2018-05-31
• Subjects: data compression -- merging; test data compression -- hierarchical block merging technique -- semiconductor device manufacturing -- integrated circuit quality -- HBMT -- test data segmentation -- test blocks categorisation -- ISCAS 89 benchmark circuits -- decoder architecture; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2017.0045
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Manufacturing of semiconductor devices at the sub‐micron level has led to the introduction of huge number of faults. To ensure the quality of integrated circuits (ICs), enormous amount of test data is needed which, in turn, increases the overall test cost of the ICs. This study presents a hierarchical block‐merging‐based technique (HBMT) for test data compression, which appropriately encodes the test pattern blocks of fixed sizes at inter‐ and intra‐block levels using lesser number of bits. The proposed technique works in four steps: segmentation of the entire length of test data into equal length blocks; categorisation of test blocks as compatible blocks and unique blocks; merging of compatible blocks to form representative pattern block, which is further merged at sub‐block level; and compression of the non‐compatible (unique) blocks using different encoding cases. Experimental results performed on various international symposium for circuits and systems (ISCAS)' 89 benchmark circuits demonstrate the effectiveness of the proposed test data compression technique. It is found that application of HBMT can improve the compression efficiency by an average of 73% along with a reduction in the test application time. This study also presents the decoder architecture.