Light‐weight configurable architecture for QRS detection. Issue 2 (18th January 2019)

• Record Type: Journal Article
• Authors: Jain, Nupur; Mishra, Biswajit
• Is Part Of: IET computers & digital techniques. Volume 13:Issue 2(2019)
• Page Start: 70
• Page End: 77
• Publication Date: 2019-01-18
• Subjects: body sensor networks -- memory architecture -- medical signal processing -- electrocardiography -- coprocessors; weight configurable architecture -- QRS detection -- gate count -- fly reconfigurability -- low‐power biomedical applications -- ExG processing -- light‐weight co‐processor -- on‐node digital signal -- image processing -- wireless sensor node -- body sensor network -- adaptive memory -- configurable data path -- on‐the‐fly -- memory structure; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2018.5084
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : In this study, the authors present a configurable architecture having gate count of ≃ 3.2 k and on the fly reconfigurability for low‐power biomedical applications such as QRS detection, ExG processing etc . The proposed architecture is a light‐weight co‐processor that supports on‐node digital signal and image processing functions potentially eliminating the power consumed by radios in wireless sensor node and body sensor network. The architecture consists of a 3 × 3 array of register units along with adaptive memory with configurable data path. The architecture can be configured on‐the‐fly for seven functions with the current memory structure. However, more number of functions can be targeted with increased memory. They demonstrate the realisation of Pan–Tompkins algorithm commonly used for QRS detection on the proposed architecture using the reconfigurability. This work offers ≈ 4 × reduced area and 2.3 × increase in performance with respect to the existing contemporary literature.