Secure distribution infrastructure for hardware digital contents. Issue 6 (1st November 2014)

• Record Type: Journal Article
• Authors: Cilardo, Alessandro; Barbareschi, Mario; Mazzeo, Antonino
• Is Part Of: IET computers & digital techniques. Volume 8:Issue 6(2014)
• Page Start: 300
• Page End: 310
• Publication Date: 2014-11-01
• Subjects: field programmable gate arrays -- cryptographic protocols -- codecs -- image coding; security‐related FPGA features -- area costs -- image codec components -- user device -- partial bitstreams -- cryptographic protocol -- trusted third‐party entity -- bitstream encryption -- FPGA devices -- security‐related features -- HDCs -- hardware core distribution -- field‐programmable gate array reconfigurability -- hardware digital contents -- secure distribution infrastructure process; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2014.0036
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Field‐programmable gate array (FPGA) reconfigurability creates the possibility of distributing hardware cores pretty much like software digital contents, possibly on payment or on a subscription basis. In this work, the authors propose an infrastructure for the secure distribution of such hardware digital contents (HDCs). Aimed at the practical realisation of the envisioned scenario, this study analyses the security‐related features of the current FPGA devices, for example, (partial) bitstream encryption, and takes them as the underlying constraints for the definition of the infrastructure. This work clearly identifies the roles involved in the secure distribution process, including a trusted third‐party entity, and introduces a cryptographic protocol ensuring the confidentiality and the trustworthiness of partial bitstreams dynamically downloaded to the user's device. This study also presents a detailed case‐study application scenario, namely the secure distribution of image codec components, providing a few quantitative results and demonstrating the limited overhead incurred by the proposed solution in terms of time and area costs. The conclusive section of this study discusses the lesson learned from this work and draws a few proposals for the evolution of security‐related FPGA features which may enable the full realisation of the secure HDC distribution concept.