Towards IP integration on SoC: a case study of high‐throughput and low‐cost wrapper design on a novel IBUS architecture. Issue 6 (18th September 2020)

• Record Type: Journal Article
• Authors: Yang, Xiaokun; Sha, Shi; Unwala, Ishaq; Lu, Jiang
• Is Part Of: IET computers & digital techniques. Volume 14:Issue 6(2020)
• Page Start: 353
• Page End: 362
• Publication Date: 2020-09-18
• Subjects: system‐on‐chip -- industrial property -- field programmable gate arrays -- logic design -- cryptographic protocols; data transfer -- IP integration -- low‐cost wrapper design -- third‐party intellectual properties -- system‐on‐chip architecture -- bus protocol -- integrated bus -- configurable bus wrapper -- bus efficiency -- resource cost -- field‐programming gate array slice count -- bus transfer -- energy consumption -- IBUS wrappers -- IBUS SoC -- block test -- cipher test -- normalised slice‐time‐power -- bridge‐based SoC integration -- AXI3‐interfaced verification IP -- IBUS architecture; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2019.0090
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : To integrate third‐party intellectual properties (IPs) into a new system‐on‐chip (SoC) architecture is a big challenge. Therefore, this study first presents a new bus protocol named as integrated bus (IBUS), and more important, a configurable bus wrapper for connecting AXI3‐interfaced IPs into IBUS is further proposed, aiming to finding the optimal balance between bus efficiency and resource cost in terms of field‐programming gate array slice count, bus transfer latency, and energy consumption. As a case study, the authors implemented three IBUS wrappers for integrating three AXI3‐interfaced verification IPs into an IBUS SoC. Experimental results show that their proposed work achieves a higher valid data throughput ( 1.35 × in the block test and 1.52 × in the cipher test) compared with the designs on conventional bridge‐based SoC integration, as well as a large reduction in the normalised slice‐time‐power (18.73% in the block benchmark and 23.45% in the cipher benchmark) when setting the same weights of slice number, data transfer latency, and energy dissipation.