A universal method for designing low‐power carbon nanotube FET‐based multiple‐valued logic circuits. Issue 4 (1st July 2013)

• Record Type: Journal Article
• Authors: Moaiyeri, Mohammad Hossein; Mirzaee, Reza Faghih; Doostaregan, Akbar; Navi, Keivan; Hashemipour, Omid
• Is Part Of: IET computers & digital techniques. Volume 7:Issue 4(2013)
• Page Start: 167
• Page End: 181
• Publication Date: 2013-07-01
• Subjects: carrier mobility -- circuit simulation -- CMOS logic circuits -- logic design -- low‐power electronics -- multivalued logic circuits -- nanoelectronics -- performance evaluation -- power aware computing -- SPICE -- ternary logic -- threshold logic -- carbon nanotube field effect transistors; low‐power carbon nanotube FET‐based multiple‐valued logic circuit design -- nanoelectronics -- low‐power MVL circuits -- CNTFET‐based MVL circuits -- CNTFET device -- threshold voltages -- carrier mobility -- N‐type devices -- P‐type devices -- high‐performance multiple‐Vth circuits -- CMOS architecture -- binary gates -- CNTFET‐based ternary circuits -- static power dissipation -- Synopsys HSPICE -- energy efficiency -- power consumption -- state‐of‐the‐art quaternary circuits -- size 32 nm; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2013.0023
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : This study presents new low‐power multiple‐valued logic (MVL) circuits for nanoelectronics. These carbon nanotube field effect transistor (FET) (CNTFET)‐based MVL circuits are designed based on the unique characteristics of the CNTFET device such as the capability of setting the desired threshold voltages by adopting correct diameters for the nanotubes as well as the same carrier mobility for the P‐ and N‐type devices. These characteristics make CNTFETs very suitable for designing high‐performance multiple‐ V th circuits. The proposed MVL circuits are designed based on the conventional CMOS architecture and by utilising inherently binary gates. Moreover, each of the proposed CNTFET‐based ternary circuits includes all the possible types of ternary logic, that is, negative, positive and standard, in one structure. The method proposed in this study is a universal technique for designing MVL logic circuits with any arbitrary number of logic levels, without static power dissipation. The results of the simulations, conducted using Synopsys HSPICE with 32 nm‐CNTFET technology, demonstrate improvements in terms of power consumption, energy efficiency, robustness and specifically static power dissipation with respect to the other state‐of‐the‐art ternary and quaternary circuits.