Power efficient error correction coding for on‐chip interconnection links. Issue 6 (1st October 2020)

• Record Type: Journal Article
• Authors: Velayudham, Sumitra; Rajagopal, Sivakumar; Venkata Ramana Rao, Yeragudipati; Ko, Seok‐Bum
• Is Part Of: IET computers & digital techniques. Volume 14:Issue 6(2020)
• Page Start: 299
• Page End: 312
• Publication Date: 2020-10-01
• Subjects: integrated circuit reliability -- error correction codes -- integrated circuit interconnections -- network‐on‐chip -- crosstalk -- Hamming codes -- low‐power electronics; power efficient error correction coding -- on‐chip interconnection links -- error correction probability tolerance -- single error correction -- double error detection -- extended Hamming code -- standard triplication error correction methods -- data stream rerouting block -- power efficiency -- link power consumption -- link swing voltage -- delay reduction -- on‐chip interconnect links -- high error correction capability -- configurable self‐calibrated power efficient five‐bit error correction code -- Synopsys tools -- UMC technology -- network‐on‐chip -- size 90.0 nm -- word length 5 bit; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2019.0082
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : A configurable self‐calibrated power efficient five‐bit error correction code is proposed to correct both single bit random and burst errors up to five bits; providing 100% error correction probability with crosstalk avoidance. It can also correct higher‐order error up to 9 bits with an error correction probability tolerance of 73% for on‐chip interconnection links. Single error correction and double error detection with extended Hamming code (22, 16) is utilised along with standard triplication error correction methods in the proposed code. Self‐calibration algorithm and data stream rerouting block are integrated into the error correction code to achieve power efficiency. Reliability, link power consumption, and link swing voltage are estimated using an analytical model used in a network‐on‐chip. Area, power, and delay of the codec are obtained using Synopsys tools utilising UMC 90 nm technology. The proposed method provides 32–73% power saving and 22.3–60.6% delay reduction with negligible area overhead compared with the state‐of‐the‐art works. Estimated results prove that it provides a 40.5–50% reduction in link swing voltage and link power consumption compared with the state‐of‐the‐art works. The proposed code is more appropriate for on‐chip interconnect links where it provides high reliability and low swing voltage with high error correction capability compared with existing codes.