Automated planning for finding alternative bug traces. Issue 6 (18th September 2020)

• Record Type: Journal Article
• Authors: Jana, Rajib Lochan; Dey, Soumyajit; Mondal, Arijit; Dasgupta, Pallab
• Is Part Of: IET computers & digital techniques. Volume 14:Issue 6(2020)
• Page Start: 322
• Page End: 335
• Publication Date: 2020-09-18
• Subjects: program debugging -- planning (artificial intelligence) -- microcomputers -- program verification; microarchitectural events -- bug traces -- automated planning -- microprocessor design -- verification engineer -- artificial Intelligence planning -- planning tool; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2019.0283
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Bug traces serve as references for patching a microprocessor design after a bug has been found. Unless the root cause of a bug has been detected and patched, variants of the bug may return through alternative bug traces, following a different sequence of micro‐architectural events. To avoid such a situation, the verification engineer must think of every possible way in which the bug may return, which is a complex problem for a modern microprocessor. This study proposes a methodology which gleans high‐level descriptions of the micro‐architectural steps and uses them in an artificial Intelligence planning framework to find alternative pathways through which a bug may return. The plans are then translated to simulation test cases which explore these potential bug scenarios. The planning tool essentially automates the task of the verification engineer towards exploring possible alternative sequences of micro‐architectural steps that may allow a bug to return. The proposed methodology is demonstrated in three case studies.