Two‐stage logarithmic converter with reduced memory requirements. Issue 1 (1st January 2014)

• Record Type: Journal Article
• Authors: Chaudhary, Mandeep; Lee, Peter
• Is Part Of: IET computers & digital techniques. Volume 8:Issue 1(2014)
• Page Start: 23
• Page End: 29
• Publication Date: 2014-01-01
• Subjects: convertors -- digital arithmetic -- field programmable gate arrays -- piecewise linear techniques -- piecewise polynomial techniques -- read‐only storage -- reconfigurable architectures; two‐stage logarithmic converter -- reduced memory requirements -- binary logarithm -- arithmetic components -- fractional precision -- uniform piecewise linear techniques -- nonuniform piecewise linear techniques -- uniform piecewise polynomial techniques -- nonuniform piecewise polynomial techniques -- ROM -- multipliers -- numeric precision -- Xilinx Spartan3 FPGA -- Xilinx Spartan6 FPGA -- reconflgurable fabric -- Spartan6 XC6SLX16 device -- logic slices -- block RAM -- normalised binary number conversion -- frequency 42.3 MHz -- frequency 127.8 MHz -- storage capacity 11.3 Kbit -- frequency 71.4 MHz -- frequency 160 MHz; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2012.0134
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : This study presents an efficient method for converting a normalised binary number x (1 ≤ x < 2) into a binary logarithm. The algorithm requires less memory and fewer arithmetic components to achieve 23 bits of fractional precision than other algorithms using uniform and non‐uniform piecewise linear or piecewise polynomial techniques and requires less than 20 kbits of ROM and a maximum of three multipliers. It is easily extensible to higher numeric precision and has been implemented on Xilinx Spartan3 and Spartan6 field programmable gate arrays (FPGA) to show the effect of recent architectural enhancements to the reconfigurable fabric on implementation efficiency. Synthesis results confirm that the algorithm operates at a frequency of 42.3 MHz on a Spartan3 device and 127.8 MHz on a Spartan6 with a latency of two clocks. This increases to 71.4 and 160 MHz, respectively, when the latency is increased to eight clocks. On a Spartan6 XC6SLX16 device, the converter uses just 55 logic slices, three multipliers and 11.3kbits of Block RAM configured as ROM.