A ROM‐less reverse RNS converter for moduli set {2q ± 1, 2q ± 3}. Issue 1 (1st January 2014)

• Record Type: Journal Article
• Authors: Jaberipur, Ghassem; Ahmadifar, HamidReza
• Is Part Of: IET computers & digital techniques. Volume 8:Issue 1(2014)
• Page Start: 11
• Page End: 22
• Publication Date: 2014-01-01
• Subjects: adders -- multiplying circuits -- pipeline arithmetic -- power aware computing -- residue number systems; pipelining -- power dissipation -- area consumption -- multioperand addition -- power‐of‐two terms -- multiplicative inverse coefficient manipulation -- conjugate grouping -- adder‐only two‐stage new CRT conversion scheme -- ROM -- Montgomery multiplier -- RNS operation -- residue number systems -- Chinese remainder theorem -- reverse conversion methods -- moduli set -- read only memory‐less reverse residue number system converter; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2012.0148
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Numerous contributions on reverse conversion methods based on the Chinese Remainder Theorem (CRT), for residue number systems (RNS), have been regularly appearing in relevant literature. Reverse conversion is known as a slow RNS operation that becomes more complicated and slower for larger moduli sets. In this study, the authors examine four previous reverse converters for moduli set ƒ = {2 q − 1, 2 q + 3, 2 q + 1, 2 q − 3}. Three of these converters heavily utilise Read Only Memories (ROM), and the other one uses a Montgomery multiplier. In order to cut the costs and improve performance, the authors propose an adder‐only two‐stage New CRT conversion scheme that uses conjugate grouping of the moduli as {{2 q ± 1, 2 q ± 3}}. Also, manipulation of multiplicative inverse coefficients that are expressed as a series of power‐of‐two terms takes place via multi‐operand addition instead of using ROMs and/or multipliers. This leads to roughly 22, 19 and 8% improvement in delay, area consumption and power dissipation, respectively, in comparison to the only previous ROM‐less design for ƒ. Moreover, use of no ROMs allows for pipelining, if desired. They also address four state‐of‐the‐art converters and compare their performance with the authors (i.e. that of ƒ), where none is faster than the proposed converter. They support their claims with analytical gate‐level comparisons and via synthesis results.