Accuracy‐aware processor customisation for fixed‐point arithmetic. Issue 1 (1st January 2016)

• Record Type: Journal Article
• Authors: Vakili, Shervin; Langlois, J.M. Pierre; Bois, Guy
• Is Part Of: IET computers & digital techniques. Volume 10:Issue 1(2016)
• Page Start: 1
• Page End: 11
• Publication Date: 2016-01-01
• Subjects: fixed point arithmetic -- application specific integrated circuits -- microprocessor chips -- optimisation -- flip‐flops; JPEG decoder -- flip‐flops -- LUT -- processor architecture -- PolyCuSP -- custom processor design -- worst case error bound -- functional unit architecture -- register files -- data type word length -- WLO -- fixed point circuit -- accuracy aware word length optimisation -- fixed point word length optimisation -- processor‐based design -- microprocessor architecture -- application specific customisation -- fixed point arithmetic -- accuracy aware processor customisation; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2014.0188
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Application‐specific customisation of micro‐processor architectures has been widely accepted as an effective way to improve the efficiency of processor‐based designs. In this work, the authors propose a new processor customisation method based on fixed‐point word‐length optimisation. Accuracy‐aware word‐length optimisation (WLO) of fixed‐point circuits is an active research area with a large body of literature. For the first time, this work introduces a method to combine the WLO with the processor customisation. The data type word‐lengths, the size of register‐files and the architecture of the functional units are the main target objectives to be optimised. Accuracy requirements, defined as the worst‐case error bound, is the key consideration that must be met by any solution. A custom processor design environment, called PolyCuSP, is used to realise the processor architecture based on the solution found in the proposed optimisation algorithm. The results achieved by evaluating five benchmark show that this method can reduce the number of necessary LUTs and flip‐flops by an average of 11.9% and 5.1%, respectively. The latency is also improved by an average of 33.4%. Moreover, the method was further examined through a case study on a JPEG decoder. The results suggest 16.2% and 56.2% reduction in area consumption and latency, respectively.