Variable length mixed radix MDC FFT/IFFT processor for MIMO‐OFDM application. Issue 1 (5th December 2017)

• Record Type: Journal Article
• Authors: Locharla, Govinda Rao; Mahapatra, Kamala Kanta; Ari, Samit
• Is Part Of: IET computers & digital techniques. Volume 12:Issue 1(2018)
• Page Start: 9
• Page End: 19
• Publication Date: 2017-12-05
• Subjects: MIMO communication -- OFDM modulation -- digital arithmetic -- fast Fourier transforms -- inverse transforms -- CMOS integrated circuits -- telecommunication scheduling; variable length mixed radix MDC FFT processor -- variable length mixed radix MDC IFFT processor -- MIMO‐OFDM application -- variable length multipath delay commutator fast Fourier transform architecture -- variable length multipath delay commutator inverse FFT architecture -- multiple input multiple system -- output orthogonal frequency division multiplexing system -- spatial streams -- IEEE 802.11ac timing requirements -- resource scheduling methodology -- hardware complexity minimisation -- stagger word length strategy -- signal‐to‐quantisation noise ratio -- twiddle coefficient storage space -- TSMC‐65 nm complementary metal oxide semiconductor technology -- power consumption -- gate count -- normalised energy -- voltage 1 V -- frequency 160 MHz; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2017.0018
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : This study presents a variable length multi‐path delay commutator fast Fourier transform (FFT)/inverse FFT (IFFT) architecture for a multiple input multiple output orthogonal frequency division multiplexing system. It supports the FFT/ IFFT lengths of 512/256/128/64 samples to process each symbol carried by eight spatial streams and achieves a speed of 160 MHz to meet the IEEE 802.11ac timing requirements. A resource scheduling methodology to minimise the hardware complexity of the design is proposed and adopted in the architecture presented. A novel stagger word length strategy is also proposed and applied to achieve the better accuracy with lesser hardware. Here, the signal to quantisation noise ratio of 57.23 dB is obtained. The twiddle coefficient storage space is significantly compressed to achieve the coefficient generation with reduced hardware. The design is implemented using the TSMC‐65 nm complementary metal oxide semiconductor technology with a supply voltage of 1 V at 160 MHz. The implementation results show that the architecture has a gate count of 3, 48, 013 with power consumption of 105.1 mW and area of 0.492 mm 2 . The hardware complexity and performance of the design are compared with earlier reported architectures. It is observed that the proposed design achieves better performance in terms of hardware complexity and normalised energy for the given specifications.