Evaluation of the soft error assessment consistency of a JIT‐based virtual platform simulator. Issue 2 (23rd February 2021)

• Record Type: Journal Article
• Authors: Abich, Geancarlo; Garibotti, Rafael; Bandeira, Vitor; da Rosa, Felipe; Gava, Jonas; Bortolon, Felipe; Medeiros, Guilherme; Moraes, Fernando G.; Reis, Ricardo; Ost, Luciano
• Is Part Of: IET computers & digital techniques. Volume 15:Issue 2(2021)
• Page Start: 125
• Page End: 142
• Publication Date: 2021-02-23
• Subjects: Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/cdt2.12017
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract: Soft error resilience has become an essential design metric in electronic computing systems as advanced technology nodes have become less robust to high‐charged particle effects. Designers, therefore, should be able to assess this metric considering several software stack components running on top of commercial processors, early in the design phase. With this in mind, researchers are using virtual platform (VP) frameworks to assess this metric due to their flexibility and high simulation performance. In this regard, herein, this goal is achieved by analysing the soft error consistency of a just‐in‐time fault injection simulator (OVPsim‐FIM) against fault injection campaigns conducted with event‐driven simulators (i.e. more realistic and accurate platforms) considering single and multicore processor architectures. Reference single‐core fault injection campaigns are performed on RTL descriptions of Arm Cortex‐M0 and M3 processors, while gem5 simulator is used to multicore Arm Cortex‐A9 scenarios. Campaigns consider different open‐source and commercial compilers as well as real software stacks including FreeRTOS/Linux kernels and 52 applications. Results show that OVPsim‐FIM is more than 1000× faster than cycle‐accurate simulators and up to 312× faster than event‐driven simulators, while preserving the soft error analysis accuracy (i.e. mismatch below to 10%) for single and multicore processors.