Synthesis and exploration of clock spines. Issue 5 (10th July 2018)

• Record Type: Journal Article
• Authors: Kim, Youngchan; Kim, Taewhan
• Is Part Of: IET computers & digital techniques. Volume 12:Issue 5(2018)
• Page Start: 241
• Page End: 248
• Publication Date: 2018-07-10
• Subjects: clock distribution networks -- clocks -- circuit optimisation -- network synthesis; clock spine exploration -- for clock spine network synthesis algorithm -- clock resources -- clock variation tolerance -- slicing floorplan optimisation problem -- SFO problem -- clock spine network structures -- postfix notation -- fast cost computation -- reduced clock power -- clock mesh structures -- benchmark circuits; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2017.0234
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : This study addresses the problem of developing a synthesis algorithm for clock spine networks, which is able to systematically explore the clock resources and clock variation tolerance. The idea is to transform the problem of allocating and placing clock spines on a plane into a slicing floorplan optimisation (SFO) problem, in which every candidate of clock spine network structures is uniquely expressed into a postfix notation to enable a fast cost computation in the SFO. As a result, the authors proposed synthesis algorithm can explore the diverse structures of the clock spine network to find globally optimal ones within acceptable run time. Through experiments with benchmark circuits, it is shown that the proposed algorithm is able to synthesise the clock spine networks with 38% reduced clock skew over the clock tree structures, even 11% reduced clock power. In addition, in comparison with the clock mesh structures, the proposed clock spine networks have comparable tolerance to clock skew variation while using considerably less clock resources, reducing clock power by 36%.