High performance and predictable memory controller for multicore mixed‐criticality real‐time systems. Issue 5 (16th July 2019)

• Record Type: Journal Article
• Authors: Dabaghi, Arezoo; Farbeh, Hamed
• Is Part Of: IET computers & digital techniques. Volume 13:Issue 5(2019)
• Page Start: 376
• Page End: 382
• Publication Date: 2019-07-16
• Subjects: system‐on‐chip -- multiprocessing systems -- power aware computing -- embedded systems -- real‐time systems; high performance -- predictable memory controller -- multicore mixed‐criticality -- real‐time systems -- multicore processors -- real‐time embedded systems -- predictability requirements as well as reduce cost -- vast majority -- multicore embedded systems -- nonfunctional requirements -- mixed‐criticality systems -- shared resources -- criticality requirements -- shared memory -- state‐of‐the‐art memory controllers -- gem5 full‐system simulator -- predictable existing controller; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2018.5031
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : Multicore processors are widely used in today's real‐time embedded systems to satisfy the performance and predictability requirements as well as reduce cost. A vast majority of multicore embedded systems are running several tasks with mixed‐criticality, in which the non‐functional requirements of the tasks are different or even conflicting. A major challenge in mixed‐criticality systems is to maximise the efficiency of shared resources while satisfying the criticality requirements. Shared memory is a key component that should be well managed and memory controller plays the main role in this case. Several memory controllers have been introduced in the literature for multicore processors. In this article, the authors performed a deep investigation on three state‐of‐the‐art memory controllers using gem5 full‐system simulator and Xilinx ISE Design Suite, and compared them in terms of predictability and performance. Then, the authors proposed a memory controller that provides the same predictability as the most predictable existing controller while improving the performance by 12.3%.