Throughput/area optimised pipelined architecture for elliptic curve crypto processor. Issue 5 (25th March 2019)

• Record Type: Journal Article
• Authors: Imran, Malik; Rashid, Muhammad; Jafri, Atif Raza; Kashif, Muhammad
• Is Part Of: IET computers & digital techniques. Volume 13:Issue 5(2019)
• Page Start: 361
• Page End: 368
• Publication Date: 2019-03-25
• Subjects: pipeline processing -- field programmable gate arrays -- public key cryptography -- digital arithmetic; elliptic curve crypto processor -- elliptic curve cryptography -- arithmetic unit -- critical path delay -- clock cycles -- point addition -- point doubling -- point multiplication computation -- area overhead -- throughput/area ratio -- throughput/area optimised pipelined architecture -- FPGA -- frequency 369.0 MHz -- frequency 357.0 MHz -- frequency 337.0 MHz -- word length 163.0 bit -- word length 233.0 bit -- word length 283.0 bit; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2018.5056
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : A pipelined architecture is proposed in this work to speed up the point multiplication in elliptic curve cryptography (ECC). This is achieved, at first; by pipelining the arithmetic unit to reduce the critical path delay. Second, by reducing the number of clock cycles (latency), which is achieved through careful scheduling of computations involved in point addition and point doubling. These two factors thus, help in reducing the time for one point multiplication computation. On the other hand, the small area overhead for this design gives a higher throughput/area ratio. Consequently, the proposed architecture is synthesised on different FPGAs to compare with the state‐of‐the‐art. The synthesis results over GF(2 m ) show that the proposed design can work up to a frequency of 369, 357 and 337 MHz when implemented for m = 163, 233 and 283 bit key lengths, respectively, on Virtex‐7 FPGA. The corresponding throughput/slice figures are 42.22, 12.37 and 9.45, which outperform existing implementations.