Self‐heating burn‐in pattern generation based on the genetic algorithm incorporated with a BACK‐like procedure. Issue 6 (1st November 2015)

• Record Type: Journal Article
• Authors: Cheng, Zuolin; Cui, Xiaole; Cui, Xiaoxin; Lee, Chung Len
• Is Part Of: IET computers & digital techniques. Volume 9:Issue 6(2015)
• Page Start: 300
• Page End: 310
• Publication Date: 2015-11-01
• Subjects: circuit testing -- divide and conquer methods -- electronic engineering computing -- genetic algorithms; self‐heating burn‐in pattern generation -- genetic algorithm -- BACK‐like procedure -- integrated circuit -- uniform node transition -- multistep strategy -- transition measure -- backtracing -- target patterns -- maximal transition count -- maximal power dissipation -- pattern sequence -- divide‐and‐conquer strategy -- IC burn‐in application; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2014.0219
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : In integrated circuit (IC) burn‐in, it is desirable to produce efficient input patterns to assist heating for circuit under test. This study proposes and demonstrates an approach which uses the genetic algorithm incorporating with a BACK‐like procedure to generate the patterns which produce the maximal and/or uniform node transition as well as power dissipation for burn‐in application. A multi‐step strategy is applied in the algorithm, and a transition measure is defined to guide the backtracing of the BACK‐like procedure, improving the efficiency in searching the target patterns. Experimental results show that the approach generates better pattern pairs which produce either the maximal transition count or the maximal power dissipation than that of all the other published results. It is also able to generate the pattern sequence which achieves more uniformly stressing, by 30% improvement statistically, for each gate of the circuit under test. The computation time, because of using a divide‐and‐conquer strategy in this approach, is also reasonable, making it useful in the practical IC burn‐in application.