SkipCache: application aware cache management for chip multi‐processors. Issue 6 (1st November 2015) - Warrier, Tripti S.; Raghavendra, Kanakagiri; Mutyam, Madhu
Abstract : With the advent of multiple cores on a single chip, it is common for the systems to have multi‐level caches. Multiple levels of cache reduce the pressure on the memory bandwidth by allowing applications to store their frequently accessed data in them. The levels of cache nearer to the core filter the locality in the application access, which can result in high miss rates at farther levels. This piece of study revolves around one question: are all levels of cache needed by all applications during all phases of their execution? The study observes the effect of 2‐level and 3‐level cache hierarchies on the performance of different applications. On the basis of this study, this study proposes an application aware cache management policy called 'SkipCache', which allows an application to choose a 2‐level or 3‐level cache hierarchy during run‐time. SkipCache dynamically tracks the applications at shared last‐level cache (LLC) to identify the applications that do not obtain advantage by using the LLC. Such applications can completely skip the LLC so that other co‐scheduled cache friendly applications can efficiently use it. Evaluation of SkipCache in a 4‐core chip multi‐processor with multi‐programmed workloads shows significant performance improvement. SkipCache is orthogonal to other cache management techniques and can be used along with other optimisation techniques to improve the system performance.