A fault‐tolerant core mapping technique in networks‐on‐chip. Issue 6 (1st November 2013)

• Record Type: Journal Article
• Authors: Khalili, Fatemeh; Zarandi, Hamid R.
• Is Part Of: IET computers & digital techniques. Volume 7:Issue 6(2013)
• Page Start: 238
• Page End: 245
• Publication Date: 2013-11-01
• Subjects: fault tolerant computing -- graph theory -- network‐on‐chip -- performance evaluation -- power aware computing; fault‐tolerant core mapping technique -- application mapping -- spare core allocation -- networks‐on‐chip -- free nonfaulty processing core -- application core graph -- performance degradation -- energy consumption overheads -- failure recovery -- spare core placement -- system fault tolerance properties -- fault injection experiments -- communication energy reduction -- performance improvement; Computers -- Periodicals; Digital electronics -- Periodicals; Computer engineering -- Periodicals; Computer architecture -- Periodicals; Computer organization -- Periodicals; 621.39
• DOI: 10.1049/iet-cdt.2013.0032
• Languages: English
• ISSNs: 1751-8601

Abstract

Abstract : This study proposes a fault‐tolerant technique on application mapping and spare core allocation in networks‐on‐chip. The proposed technique sets the place of spare cores among free non‐faulty processing cores, dynamically. Here, dynamically setting means that the places of spare cores are tuned for each application and are not fixed in the platform statically. Some vertices of each application core graph can be known as critical, based on their vulnerabilities, the performance degradation and the energy consumption overheads because of negative impacts of failure recovery. This technique locates the spare cores near to the critical cores. As the main theoretical contribution, the problem of spare core placement and its impression on system fault‐tolerance properties is discussed. Some metrics are investigated to be considered in spare core allocation. The results of 1 000 000 fault injection experiments show that the proposed technique leads to communication energy reductions and performance improvement, compared with related works.