VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders. (5th July 2012)

• Record Type: Journal Article
• Authors: Passas, Georgios; Freear, Steven
• Other Names: Yan Zhiyuan Academic Editor.
• Is Part Of: Journal of electrical and computer engineering. Volume 2012(2012)
• Publication Date: 2012-07-05
• Subjects: Computer engineering -- Periodicals; Electrical engineering -- Periodicals; 621.3905
• DOI: 10.1155/2012/614259
• Languages: English
• ISSNs: 2090-0147

Abstract

Abstract : The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO) unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.