23 µW 8.9‐effective number of bit 1.1 MS/s successive approximation register analog‐to‐digital converter with an energy‐efficient digital‐to‐analog converter switching scheme. Issue 8 (28th August 2014)

• Record Type: Journal Article
• Authors: Sun, Lei; Ko, Chi Tung; Ho, Marco; Ng, Wai Tung; Leung, Ka Nang; Choy, Chiu Sing; Pun, Kong Pang
• Is Part Of: Journal of engineering. Volume 2014:Issue 8(2014)
• Page Start: 420
• Page End: 425
• Publication Date: 2014-08-28
• Subjects: analogue‐digital conversion -- digital‐analogue conversion -- CMOS digital integrated circuits; bit effective number -- successive approximation register analog‐to‐digital converter -- energy‐efficient digital‐to‐analog converter switching scheme -- split‐most significant bit capacitor array -- least significant bit‐down switching scheme -- binary‐weighted capacitor array -- area reduction -- average switching energy reduction -- capacitor matching requirement -- complementary metal oxide semiconductor process -- peak signal‐to‐distortion‐and‐noise ratio -- effective resolution bandwidth -- figure‐of‐merit -- power 23 muW -- word length 8.9 bit -- size 0.13 mum -- voltage 1 V -- voltage 0.5 V; Engineering -- Periodicals; Engineering; Electronic journals; Periodicals; 620.005
• DOI: 10.1049/joe.2014.0137
• Languages: English
• ISSNs: 2051-3305

Abstract

Abstract : This study presents a successive approximation register analog‐to‐digital converter with an energy‐efficient switching scheme. A split‐most significant bit capacitor array is used with a least significant bit‐down switching scheme. Compared with the conventional binary‐weighted capacitor array, it reduces the area and average switching energy by 50 and 87% under the same unit capacitor. Moreover, capacitor matching requirement is relaxed by 75%. A prototype design was fabricated in a 0.13 µm complementary metal oxide semiconductor process. It consumes 23.2 µW under 1 V analog supply and 0.5 V digital supply. Measured results show a peak signal‐to‐distortion‐and‐noise ratio of 55.2 dB and an effective resolution bandwidth up to 1.1 MHz when it operates at 1.1 MS/s. Its figure‐of‐merit is 44.1 fJ / conversion‐step.