FPGA‐based reconfigurable matrix inversion implementation for inverse filtering of multi‐channel SAR imaging. Issue 21 (4th November 2019)

• Record Type: Journal Article
• Authors: Li, HuiXing; Feng, YangKai; Hu, ShanQing; Li, BingYi; Xie, YiZhuang; Wu, MengChao
• Is Part Of: Journal of engineering. Volume 2019:Issue 21(2019)
• Page Start: 8027
• Page End: 8031
• Publication Date: 2019-11-04
• Subjects: microprocessor chips -- filtering theory -- field programmable gate arrays -- floating point arithmetic -- radar imaging -- synthetic aperture radar -- iterative methods -- matrix inversion -- image sampling -- pipeline processing -- processor scheduling -- resource allocation -- reconfigurable architectures; FPGA‐based reconfigurable matrix inversion implementation -- multichannel SAR imaging -- multichannel synthetic aperture radar -- virtual points -- inverse filter algorithm -- matrix inversion method -- LU decomposition algorithm -- hierarchical iterative processing strategy -- reconfigurable storage -- computing unit -- azimuthal nonuniform sampling results -- multichannel preprocessing -- floating‐point IP cores -- single‐precision floating‐point data type -- resource balancing -- reusable structure -- pipeline technology -- data scheduling -- Modelsim platform; Engineering -- Periodicals; Engineering; Electronic journals; Periodicals; 620.005
• DOI: 10.1049/joe.2019.0748
• Languages: English
• ISSNs: 2051-3305

Abstract

Abstract : In multi‐channel synthetic aperture radar (SAR), the azimuth non‐uniform sampling tends to result in a large number of virtual point targets, which are not expected. Inverse filter algorithm provides a new idea for solving this problem. This way can be abstracted as a matrix inversion in essence, which becomes the key factor that affects the real‐time and accuracy of multi‐channel pre‐processing. This study presents the implementation of matrix inversion method on field programmable gate array (FPGA), based on lower and upper triangular matrix (LU) decomposition algorithm. In this process, the efficient parallelism of FPGA and the rich floating‐point intellectual property (IP) cores are fully utilised to speed up the process of inverting the matrix with a data type of 32‐bit single‐precision floating‐point. In this design, the parallelism of the algorithm was fully considered and a hierarchical iterative processing strategy was adopted to realise the reconfigurable storage and computing unit both. At the same time, in order to achieve the balance of resources and efficiency, a reusable structure was proposed also, using the pipeline technology and appropriate data scheduling. Finally, Modelsim platform is used to observe the simulation results, and the performance can be detected combined with MATLAB platform. At last, the computational accuracy is up to 10 − 7, and the speedup ratio can reach about 1.461 × 10 3 .