Improved dual sided doped memristor: modelling and applications. Issue 5 (29th May 2014)

• Record Type: Journal Article
• Authors: Shrivastava, Anup; Khalid, Muhammad; Singh, Komal; Singh, Jawar
• Is Part Of: Journal of engineering. Volume 2014:Issue 5(2014)
• Page Start: 219
• Page End: 226
• Publication Date: 2014-05-29
• Subjects: memristors -- frequency response -- semiconductor device models -- logic gates; dual sided doped memristor -- electronic device -- frequency response -- saturation length -- device structure -- active layers -- nonlinear ionic drift model -- Iâ€"V characteristics -- circuit level simulation -- SPICE model -- logic gates -- hybrid complementary metal oxide semiconductor memristive logic -- memristor ratioed logic -- noise margin -- delay time -- dynamic hazards -- single active layer memristors; Engineering -- Periodicals; Engineering; Electronic journals; Periodicals; 620.005
• DOI: 10.1049/joe.2013.0265
• Languages: English
• ISSNs: 2051-3305

Abstract

Abstract : Memristor as a novel and emerging electronic device having vast range of applications suffer from poor frequency response and saturation length. In this paper, the authors present a novel and an innovative device structure for the memristor with two active layers and its non‐linear ionic drift model for an improved frequency response and saturation length. The authors investigated and compared the I–V characteristics for the proposed model with the conventional memristors and found better results in each case (different window functions) for the proposed dual sided doped memristor. For circuit level simulation, they developed a SPICE model of the proposed memristor and designed some logic gates based on hybrid complementary metal oxide semiconductor memristive logic (memristor ratioed logic). The proposed memristor yields improved results in terms of noise margin, delay time and dynamic hazards than that of the conventional memristors (single active layer memristors).