Modeling the threshold voltage of core-and-outer gates of ultra-thin nanotube Junctionless-double gate-all-around (NJL-DGAA) MOSFETs. (July 2021) - Kumar, Nitish; Purwar, Vaibhav; Awasthi, Himanshi; Gupta, Rajeev; Singh, Kunal; Dubey, Sarvesh
Abstract: The present article deals with the analytical modeling of threshold voltage of an ultra-thin nanotube Junctionless double-gate-all-around (NJL-DGAA) metal-oxide-semiconductor field-effect-transistor (MOSFET). Under the condition of full depletion, the modeling of the surface potential relating to inner and outer gates of the device has been performed by solving three-dimensional Poisson's equation in cylindrical coordinates with appropriate boundary conditions. Corresponding to inner and outer channel potential expressions, the two different threshold voltages of the device are obtained. Moreover, the connection between the source-to-drain subthreshold current and threshold voltage is investigated. The drain-induced-barrier-lowering (DIBL) as an indicator of short-channel effects has been studied. Further, the quantum confinement effects have been explored through quantum mechanical correction in the threshold voltage model. The model outcomes are compared with data extracted from ATLAS™ TCAD simulations, and good acceptances have been observed.