Online placement and scheduling algorithm for reconfigurable cells in self-repairable field-programmable gate array systems. (April 2018)

• Record Type: Journal Article
• Authors: C, Pradeep; Eapen, Madhuri Elsa; P P, Joby; J Kizhakkethottam, Jubilant
• Is Part Of: Computers & electrical engineering. Volume 67(2018)
• Page Start: 836
• Page End: 850
• Publication Date: 2018-04
• Subjects: Relocation -- Reconfigurable modules -- Self-repair -- Placement algorithm -- FPGA -- Dynamic runtime partial reconfiguration; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2018.02.001
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: Most of the high-end very-large-scale integration- (VLSI-) based systems use a field-programmable gate array (FPGA) as their core component. As the complexity of systems increases, the chances of fault occurrence also increase. For systems that are part of safety-critical and mission-critical applications, even a single fault can result in entire mission failure. Fault tolerance techniques need to be installed in such systems to ensure reliable, prolonged operation in spite of fault occurrence. The level of fault tolerance exhibited in nature is very remarkable. Scientists are trying to reach that level of fault tolerance in the electronics world as well, which is not always completely acquirable. Basically, fault tolerance in an FPGA is achieved by the use of spare modules, which leads to high area overheads and routing complexity. The higher the number of faults to be handled, the greater the number of spares that will be required. Partial reconfiguration has always been a proven technique to improve the efficiency and flexibility of FPGAs. This paper discusses a multiple-fault repair algorithm for FPGA-based reconfigurable systems, using dynamic runtime partial reconfiguration, in order to relocate faulty modules. Three variants or cases of repair using the algorithm are discussed and demonstrated, namely, placement with the best resource utilization, placement with the least routing overhead, and a case to generate continuous free space for the relocation of a faulty module. The main advantage of the algorithm is its flexibility, which means that it can be used according to user demands and system lifetime requirements. Maximum care is taken to eliminate chances of an unrepaired fault or a repair that degrades the performance of the system. The algorithm can handle multiple permanent faults with the best resource utilization and the least overheads. The performance of the algorithm is analyzed quantitatively, while a comparison is made with some previous studies in the literature to justify the algorithm efficiency.