A Very Compact AES-SPIHT Selective Encryption Computer Architecture Design with Improved S-Box. (31st July 2013)

• Record Type: Journal Article
• Authors: Kong, Jia Hao; Ang, Li-Minn; Seng, Kah Phooi
• Other Names: Grasso Alfio D. Academic Editor.
• Is Part Of: Journal of engineering. Volume 2013(2013)
• Publication Date: 2013-07-31
• Subjects: Engineering -- Periodicals; 620.005
• DOI: 10.1155/2013/785126
• Languages: English
• ISSNs: 2314-4904

Abstract

Abstract : The "S-box" algorithm is a key component in the Advanced Encryption Standard (AES) due to its nonlinear property. Various implementation approaches have been researched and discussed meeting stringent application goals (such as low power, high throughput, low area), but the ultimate goal for many researchers is to find a compact and small hardware footprint for the S-box circuit. In this paper, we present our version of minimized S-box with two separate proposals and improvements in the overall gate count. The compact S-box is adopted with a compact and optimum processor architecture specifically tailored for the AES, namely, the compact instruction set architecture (CISA). To further justify and strengthen the purpose of the compact crypto-processor's application, we have also presented a selective encryption architecture (SEA) which incorporates the CISA as a part of the encryption core, accompanied by the set partitioning in hierarchical trees (SPIHT) algorithm as a complete selective encryption system.