Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA. (3rd April 2013)

• Record Type: Journal Article
• Authors: Rajapaksha, Nilanka; Edirisuriya, Amila; Madanayake, Arjuna; Cintra, Renato J.; Onen, Dennis; Amer, Ihab; Dimitrov, Vassil S.
• Other Names: Strollo Antonio G. M. Academic Editor.
• Is Part Of: Journal of electrical and computer engineering. Volume 2013(2013)
• Publication Date: 2013-04-03
• Subjects: Computer engineering -- Periodicals; Electrical engineering -- Periodicals; 621.3905
• DOI: 10.1155/2013/834793
• Languages: English
• ISSNs: 2090-0147

Abstract

Abstract : Transformation and quantization play a critical role in video codecs. Recently proposed algebraic-integer-(AI-) based discrete cosine transform (DCT) algorithms are analyzed in the presence of quantization, using the High Efficiency Video Coding (HEVC) standard. AI DCT is implemented and tested on asynchronous quasi delay-insensitive logic, using Achronix SPD60 field programmable gate array (FPGA), which leads to lower complexity, higher speed of operation, and insensitivity to process-voltage-temperature variations. Performance of AI DCT with HEVC is measured in terms of the accuracy of the transform coefficients and the overall rate-distortion (R-D) characteristics, using HM 7.1 reference software. Results indicate a 31% improvement over the integer DCT in the number of transform coefficients having error within 1%. The performance of the 65 nm asynchronous hardware in terms of speed of operation is investigated and compared with the 65 nm synchronous Xilinx FPGA. Considering word lengths of 5 and 6 bits, a speed increase of 230% and 199% is observed, respectively. These results indicate that AI DCT can be potentially utilized in HEVC for applications demanding high accuracy as well as high throughput. However, novel quantization schemes are required to allow the accuracy improvements obtained.