Configurable Transmitter and Systolic Channel Estimator Architectures for Data-Dependent Superimposed Training Communications Systems. (27th December 2012)

• Record Type: Journal Article
• Authors: Romero-Aguirre, E.; Parra-Michel, R.; Carrasco-Alvarez, Roberto; Orozco-Lugo, A. G.
• Other Names: Cumplido René Academic Editor.
• Is Part Of: International journal of reconfigurable computing. Volume 2012(2012)
• Publication Date: 2012-12-27
• Subjects: Adaptive computing systems -- Periodicals; Adaptive computing systems; Periodicals; 004
• DOI: 10.1155/2012/236372
• Languages: English
• ISSNs: 1687-7195

Abstract

Abstract : In this paper, a configurable superimposed training (ST)/data-dependent ST (DDST) transmitter and architecture based on array processors (APs) for DDST channel estimation are presented. Both architectures, designed under full-hardware paradigm, were described using Verilog HDL, targeted in Xilinx Virtex-5 and they were compared with existent approaches. The synthesis results showed a FPGA slice consumption of 1% for the transmitter and 3% for the estimator with 160 and 115 MHz operating frequencies, respectively. The signal-to-quantization-noise ratio (SQNR) performance of the transmitter is about 82 dB to support 4/16/64-QAM modulation. A Monte Carlo simulation demonstrates that the mean square error (MSE) of the channel estimator implemented in hardware is practically the same as the one obtained with the floating-point golden model. The high performance and reduced hardware of the proposed architectures lead to the conclusion that the DDST concept can be applied in current communications standards.