Broadband linearity enhancement method for a 1.3 GHz–2.5 GHz digitally-assisted oscillator in a 55-nm CMOS technology. (July 2021)

• Record Type: Journal Article
• Authors: Fang, Yun; Tang, Zhong; Yu, Xiao-Peng; Xu, Zhiwei; Gao, Hao
• Is Part Of: Microelectronics journal. Volume 113(2021)
• Publication Date: 2021-07
• Subjects: Linearity -- Ring oscillator -- Digitally-assisted oscillator -- Digital array radar; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105103
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: At the L/S band, the digital array radars with digital beam-forming characteristics require a compact RF module for a plane array. Such an RF module would require a small-sized local clock generation to synchronize with the central distributed clock signal. This paper proposes a 0.04 mm 2, broadband local clock generation for the RF module in digital array radar. In such a multi-band digital array radar, the linearity of the clock generator is a bottleneck. A linearity enhanced algorithm for switched-capacitor digitally-assisted oscillators is proposed in this paper. In this linearity enhancement technique, a calibration resistor array is used to improve frequency-tuning characteristics. The digitally-assisted oscillator has a highly linearized frequency tuning curve without demanding much more power and silicon area. A prototype is fabricated using a 55-nm CMOS process. From measurement, it has a frequency tuning range from 1.3 GHz to 2.5 GHz while occupying 225 × 180 μm 2 . The measured coarse bank tuning maximum DNL is 0.39 LSB, and the maximum INL is 4.64 LSB, which has been reduced to 43% of the other state-of-art work. The maximum power consumption is 15.8 mW from a 1.2 V supply voltage.