CNTFET design of a multiple-port ternary register file. (July 2021)

• Record Type: Journal Article
• Authors: Mohammaden, Amr; Fouda, Mohammed E.; Alouani, Ihsen; Said, Lobna A.; Radwan, Ahmed G.
• Is Part Of: Microelectronics journal. Volume 113(2021)
• Publication Date: 2021-07
• Subjects: Ternary logic gates -- CNTFET -- Latch -- Flip flop -- Dynamic D-latch -- CNTEFT D-latch; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2021.105076
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Ternary number system offers higher information processing within the same number of digits when compared to binary systems. Such advantage motivated the development of ternary processing units especially with CNTFET which offers better power and delay results compared to CMOS-based realization. In this paper, we propose a variety of circuit realizations for the ternary memory elements that are needed in any processor including ternary D-latch, and ternary D-flip-flop. These basic building blocks are then used to design a ternary register file with multiple read and write ports. This paper is an attempt to investigate the performance aspects of using ternary RF to open the gate of more contributions and research in the direction of full ternary computer architecture. The proposed designs have been compared in terms of power, area, and latency at different supply voltages and operating temperatures.