FPGA based implementation of reversible data hiding scheme for content verification and quality access control of image. (17th September 2021)

• Record Type: Journal Article
• Authors: Jana, Poulami; Phadikar, Amit; Mandal, Himadri
• Is Part Of: International journal of signal and imaging systems engineering. Volume 12:Number 3(2021)
• Page Start: 93
• Page End: 107
• Publication Date: 2021-09-17
• Subjects: content dependent watermarking -- access control -- DCT -- discrete cosine transform -- VHDL -- very-high-speed-integrated-circuit-hardware-description-language -- FPGA -- field-programmable-gate-array; Signal processing -- Periodicals; Imaging systems -- Periodicals; Information theory -- Periodicals; 621.3822
• Languages: English
• ISSNs: 1748-0698

Abstract

Reversible watermarking (RW) is the type of lossless data-hiding technique where the original object can be retrieved pixel by pixel at the receiver. This paper represents the hardware design for the spread spectrum (SS) based content-dependent RW in the Discrete Cosine Transform (DCT) domain for quality access control of digital image. The watermark is generated from DCT coefficients of a set of blocks (8 × 8) selected by a secret key. It is inserted into another set of DCT blocks (8×8) using SS modulation. In the decoder, the original watermark is generated and extracted by the secret key. The RW system is investigated in very-large-scale-integration with field-programmable-gate-array for real-time implementation of (N × N) image block. The framework is judged and verified about device utilisation parameters, power consumption, and bit rate. The encoder and decoder achieve the highest average throughput of 79.7025 Megabyte/s. This design also saves 88.46% more power than the related works.