Enabling heterogeneous ray‐tracing acceleration in edge/cloud architectures. (16th July 2020)

• Record Type: Journal Article
• Authors: Sampaio, Adrianno A.; Sena, Alexandre C.; Nery, Alexandre S.
• Other Names: Wang Zhibo guestEditor.; Jiang Lin guestEditor.; Suman Bilial guestEditor.; Wyrzykowski Roman guestEditor.; Szymanski Boleslaw K. guestEditor.; Bentes Cristiana Barbosa guestEditor.; França Felipe M.G. guestEditor.; Marzulo Leandro Augusto Justen guestEditor.; Mencagli Gabriele guestEditor.; Pilla Mauricio Lima guestEditor.
• Is Part Of: Concurrency and computation. Volume 33:Number 11(2021)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2020-07-16
• Subjects: ARM -- edge/cloud computing -- FPGA accelerator -- heterogeneous -- MPSoC; Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.5822
• Languages: English
• ISSNs: 1532-0626

Abstract

Summary: The ray‐tracing algorithm is very costly regarding time complexity and while many techniques have been conceived over the years with the purpose of accelerating its execution, one stands out: parallelism exploitation of ray‐triangle intersection operations. In this sense, field‐programmable gate arrays (FPGAs) have plenty resources to run specialized accelerators that execute multiple operations in parallel. Moreover, modern FPGAs are embedded with multiprocessor systems‐on‐chip based on ARM architecture, which can be used simultaneously with the FPGA programmable logic to further accelerate the application execution. In this work, we present and analyze a reconfigurable accelerator for ray‐tracing specialized in computing ray‐triangle intersections at the network edge of a heterogeneous cloud computing environment. The accelerator is specified using Xilinx high‐level synthesis and is implemented in a Xilinx Zynq FPGA (XC7Z020‐1CLG400C). We also present an execution model which enables the exploitation of the available computing elements of the heterogeneous system: ARM Cortex‐A53, FPGA programmable logic, and cloud machines. Experimental performance and synthesis results show that the heterogeneous system can efficiently render a simplified version of the Stanford Bunny model when using the hardware accelerator with up to six instances of a ray‐triangle intersection unit together with the other computing resources.