Hardware Architecture Design for WSN Runtime Extension. (28th April 2013)

• Record Type: Journal Article
• Authors: Asensio, Ángel; Blasco, Rubén; Marco, Álvaro; Casas, Roberto
• Other Names: Wang Ling Academic Editor.
• Is Part Of: International journal of distributed sensor networks. (2013)
• Publication Date: 2013-04-28
• Subjects: Sensor networks -- Periodicals; Intelligent agents (Computer software) -- Periodicals; Multisensor data fusion -- Periodicals; 681.2
• DOI: 10.1155/2013/136745
• Languages: English
• ISSNs: 1550-1329

Abstract

Abstract : Internet of Things imposes demanding requirements on wireless sensor networks as key players in context awareness procurement. Temporal and spatial ubiquities are one of the essential features that meet technology boundaries in terms of energy management. Limited energy availability makes anywhere and anytime sensing a challenging task that forces sensor nodes to wisely use every bit of available power. One of the earliest and most determining decisions in the electronic design stage is the choice of the silicon building blocks that will conform hardware architecture. Designers have to choose between dual architectures (based on a low-power microcontroller controlling a radio module) and single architectures (based on a system on chip). This decision, together with finite state machine design and application firmware, is crucial to minimize power consumption while maintaining expected sensor node performance. This paper provides keys for energy analysis of wireless sensor node architecture according to the specific requirements of any application. It thoroughly analyzes pros and cons of dual and single architectures providing designers with the basis to select the most efficient for each application. It also provides helpful considerations for optimal sensing-system design, analyzing how different strategies for sensor measuring and data exchanging affect node energy consumption.