36 μW fourth order sigma-delta modulator using single operational amplifier. Issue 2 (3rd April 2021) - Sharma, Vivek; Kumar Y.B., Nithin; M.H., Vasantha
ABSTRACT: This paper presents a single loop fourth-order Discrete-Time Sigma-Delta Modulator (ΣΔM) using single Operational Amplifier (Op-Amp). Proposed ΣΔM utilises delay-based discrete-time integrators and an Op-Amp to implement all the integrators. Op-Amp reuse helps in saving power. A switched-capacitor based proposed design is simulated in standard 180 nm CMOS technology with an effective resolution of 12.04 bits. The proposed ΣΔM achieves a Signal to Noise Distortion Ratio (SNDR) of 74.24 dB with 78 dB of Dynamic Range (DR). An input signal of −4 dBFS magnitudes and 1.125 kHz of frequency is sampled at a sampling frequency of 320 kHz. The proposed circuit is designed for 10 kHz Bandwidth (BW) with Oversampling Ratio (OSR) of 16. The proposed modulator achieves Figure-of-Merit (FOM) of 158.68 dB/0.427 (pJ/conversion-step) with a total power consumption of 36 µ W at 1.8 V supply voltage. The layout area of the proposed circuit is 134 µ m ×134 µ m.