Layer‐Controlled Low‐Power Tunneling Transistors Based on SnS Homojunction. Issue 5 (2nd April 2021) - Liang, Jiakun; Li, Hong; Liu, Fengbin; Lu, Jing
Abstract: Utilizing the layer‐controlled bandgap of a 2D material is an effective way of improving a tunneling field‐effect transistor (TFET) device's performance because of the narrowing tunneling barrier. An ab initio quantum transport method is used to study the SnS homojunction TFETs at a sub‐10 nm scale through layer controlling. The optimal SnS homojunction TFET has a bilayer SnS as the source electrode, which possesses a low leakage current like the ML SnS TFET and a high on‐state current like the BL SnS TFET. The low SS ave_4dec (subthreshold swing over four decades of the drain currents) of ≈47–48 mV dec −1 and I 60 (drain current at 60 mV dec −1 ) of ≈1.1–1.2 µA µm −1 implies the BL source SnS TFET, a fast low‐power (LP) device. The optimal BL source SnS TFET with a gate length of L g  = 10 nm exceeds the LP device requirement of the International Technology Roadmap for Semiconductors (ITRS) (2013 version), and its negative capacitance counterparts can exceed the ITRS 2028 target for LP device at L g  = 5 nm. Abstract : Utilizing a layer‐controlled bandgap, sub‐10 nm SnS homojunction tunneling field‐effect transistors (TFETs) are simulated with bilayer SnS as source electrode. The optimal BL source SnS TFET with L g  = 10 nm possesses a sub‐thermionic SS ave_4dec and a high I 60 and exceeds the International Technology Roadmap for Semiconductors (ITRS) low‐power (LP) device requirement. Its negative capacitance counterparts exceed the ITRS LP target at L g  = 5 nm.