Design of zero bias power detectors towards power consumption optimization in 5G devices. (May 2021) - Alaji, Issa; Aouimeur, Walid; Ghanem, Haitham; Okada, Etienne; Lépilliet, Sylvie; Gloria, Daniel; Ducournau, Guillaume; Gaquière, Christophe
Abstract: This paper presents the design and characterization of zero bias power detectors, based on MOSFET transistors, integrated in SiGe 55-nm BiCMOS technology from ST-Microelectronics. The working frequency bands of the circuits are located in the range (38–55) GHz, dedicated to optimize the power consumption in 5G devices. Three NMOS categories available in the technology are used (GP, LP, HPA), the aim is to design several detectors based on different NMOS categories in order to compare their performances. In addition, a detector based on a stack of 6 LP transistors is designed in order to increase the dynamic range. Compared to recent works, the HPA detector exhibits a very good performance with very low noise equivalent power value (NEP) 3.8 pW/ H z and large dynamic range of 67 ​dB. The extracted voltage sensitivity values of these detectors are between (850–1400) V/W showing good agreements with the simulation results.