Field-programmable gate arrays in a low power vision system. (March 2021)

• Record Type: Journal Article
• Authors: P., Suresh; U., Saravanakumar; Iwendi, Celestine; Mohan, Senthilkumar; Srivastava, Gautam
• Is Part Of: Computers & electrical engineering. Volume 90(2021)
• Publication Date: 2021-03
• Subjects: Ultrascale -- Low power -- Computer vision application -- Dynamic partial reconfiguration; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2021.106996
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: In recent years, field-programmable gate arrays have played a major role in developing low power electronic systems. End users usually prefer systems with high performance, reduced size, and low power consumption. These requirements create a challenging task for designers. Re-configuring technology allows the use of field-programmable gate arrays to be at the maximum level during runtime. This paper proposes the implementation of the Dynamic Partial Reconfiguration technique to switch during runtime between two edge detection algorithms (FASTX and Sobel) in a computer vision algorithm. Xilinx Ultrascale+ZCU106 has been used as the implementation target since it consumes approximately 4% less power during runtime. It was discovered that the dynamic switching between algorithms reduces the on-chip area utilization. Finally, through experimental results our proposed work has demonstrated the applicability of computer vision with low power consumption. Graphical abstract: Highlights: Reconfiguring technology allows the use of FPGA at the maximum level during runtime Dynamic Partial Reconfiguration technique is implemented to maximize edge detection System consumes approximately 4% less power during runtime. Dynamic switching between the algorithms reduces the on-chip area utilization. The application of computer vision with low power consumption was realized.