A new floating-point adder FPGA-based implementation using RN-coding of numbers. (March 2021) - Araujo, Túlio; Cardoso, Matheus B.R.; Nepomuceno, Erivelton G.; Llanos, Carlos H.; Arias-Garcia, Janier
Abstract: A well-known problem in the computer science area is related to numerical data representation, which directly affects adder circuits' design and a reason to have different formats: IEEE Std. 754, Half-Unit-Biased (HUB), and Round-to-Nearest (RN). RN has an advantage that rounding to nearest is equivalent to a word truncation. It avoids double rounding errors and intermediate rounding steps with an exact conversion between formats, making it applicable to general problems. However, there is a lack of research on the hardware implementation of the RN representation. In this work, we propose hardware architectures for binary and floating-point adders, analyzing for the latter its performance in terms of error and resource consumption in FPGAs. To accomplish this, we have developed a one-bit RN-based adder that allows modular designs, considering an efficient signal propagation to obtain new architectures for both binary and floating-point single-precision adders. The results open new perspectives for further applications. Graphical abstract: Highlights: RN has an advantage that rounding to nearest is equivalent to a word truncation. Round-off errors are frequently found when the IEEE Std. 754 format is used. The problem arises when a more/less precise representation is necessary to maintain the accuracy/silicon area specifications. This work explores new hardware architectures for binary and floating-point adders based on numbers' RN-coding. A new floating-point adder which could be appropriate for fused data-path operations is proposed.