Efficient sign identification engines for integers represented in RNS extended 3‐moduli set {2n− 1, 2n+k, 2n + 1}. Issue 16 (1st July 2014)

• Record Type: Journal Article
• Authors: Sousa, L.; Martins, P.
• Is Part Of: Electronics letters. Volume 50:Issue 16(2014)
• Page Start: 1138
• Page End: 1139
• Publication Date: 2014-07-01
• Subjects: residue number systems -- set theory -- signal detection -- CMOS integrated circuits -- fixed point arithmetic -- digital signal processing chips; sign identification engine -- RNS -- 3‐moduli set -- digital fixed point signal processing -- residue number system -- binary channel width -- hardware architecture -- CMOS technology -- size 65 nm; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2014.2029
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : Sign detection is a widely used operation, namely in digital fixed‐point signal processing, but hard to perform in residue number systems (RNSs). Presented is an effective method for performing RNS sign identification in the comprehensive extended 3‐moduli set {2 n − 1, 2 n + k, 2 n + 1}, which covers from the traditional 3‐moduli set, for k = 0, up to the set whose binary channel width is 2 n ( k = n ). The proposed method is applied to design an efficient hardware architecture for sign detection that not only takes advantage of the arithmetic units available in the RNS, but also imposes a small overhead, both in terms of cost and performance. Experimental results for a 65 nm CMOS technology show that the proposed architecture supersedes the related state‐of‐the‐art, requiring < 40% of circuit area, reducing the imposed delay by about 25%, and the power consumption by 30%.