67 dB SNDR 20 kHz BW SC third‐order ∑Δ modulator with single Op‐Amp and 20 µW power consumption for bio‐medical applications. Issue 6 (7th September 2020)

• Record Type: Journal Article
• Authors: Sharma, Vivek; Kumar Y.B., Nithin; M.H., Vasantha
• Is Part Of: IET circuits, devices & systems. Volume 14:Issue 6(2020)
• Page Start: 881
• Page End: 891
• Publication Date: 2020-09-07
• Subjects: sigma‐delta modulation -- low‐power electronics -- switched capacitor networks -- transfer functions -- operational amplifiers -- CMOS integrated circuits -- biomedical electronics -- Monte Carlo methods; single operational amplifier -- single op‐amp -- delay‐based design -- relaxed integrator -- power consumption -- third‐order noise transfer function -- single main clock -- single‐loop third‐order discrete‐time sigma–delta modulator -- third‐order ∑Δ modulator -- bio‐medical applications -- delay‐based discrete‐time integrators -- power performance metric -- low power dissipation -- analogue feed‐forward path -- local feedback loop -- switched capacitor op‐amp -- CMOS technology -- Monte Carlo simulation -- frequency 20.0 kHz -- size 180.0 nm -- word length 10.75 bit -- frequency 2.125 kHz -- frequency 1.024 MHz -- power 20.0 muW -- voltage 1.8 V -- size 95.0 mum -- size 100.0 mum; Electronic circuits -- Periodicals; Electronic systems -- Periodicals; 621.381505
• DOI: 10.1049/iet-cds.2019.0414
• Languages: English
• ISSNs: 1751-858X

Abstract

Abstract : This paper presents a single loop 3 rd order discrete‐time Sigma–Delta Modulator ( ∑ Δ M ) using a single operational amplifier (Op‐Amp). The proposed ∑ Δ M utilises delay‐based discrete‐time integrators and a single Op‐Amp is used to implement all the integrators of the proposed design. The delay‐based design helps in relaxing the settling time requirement of an integrator, also the error due to slewing in the output of the integrator is avoided. A switched capacitor Op‐Amp based proposed design is simulated in standard 180~nm CMOS technology with a resolution of 10.75 bits. The proposed ∑ Δ M achieves a signal‐to‐noise‐distortion ratio (SNDR) of 66.48 dB and dynamic range (DR) of 70 dB. An input signal of −4 dBFS magnitude at a frequency of 2.125 kHz is sampled with a sampling frequency of 1.024 MHz. The proposed circuit is designed for a bandwidth (BW) of 20 kHz with an over‐sampling‐ratio (OSR) of 25.6. The proposed modulator achieves a figure‐of‐merit (FOMS/FOMW) of 156.48 dB/0.290 (pJ/conversion‐step) with the total power consumption of 20 µW at 1.8 V supply voltage (VDD). A Monte‐Carlo simulation for the SNDR of the proposed design is done and the achieved mean and standard deviation (SD) is 66.09 dB and 1.025 respectively for 1000 samples.