Scaling down of cobalt quantum‐dots by colloidal route for non‐volatile memory device application. (23rd October 2019)

• Record Type: Journal Article
• Authors: Yadav, Manoj; Velampati, Ravi Shankar R.; Mandal, Debaprasad
• Is Part Of: Micro & nano letters. Volume 14:Number 12(2019)
• Page Start: 1274
• Page End: 1277
• Publication Date: 2019-10-23
• Subjects: semiconductor quantum dots -- colloids -- silicon compounds -- random‐access storage -- integrated circuit measurement -- low‐power electronics -- cobalt; SiO2 -- Co -- voltage 0.35 V to 4.0 V -- size 1.0 nm to 2.0 nm -- retention characteristics -- C–t measurements -- capacitance–time measurements -- C–V measurements -- capacitance–voltage measurements -- floating‐gate NVM device fabrication -- scaled‐down colloidal cobalt QDs -- cobalt quantum‐dot synthesis -- floating gate memory device -- low power NVM applications -- sweep voltages -- nonvolatile memory device application -- colloidal route; Nanotechnology -- Periodicals; Nanostructures -- Periodicals; Microtechnology -- Periodicals; 620.5
• DOI: 10.1049/mnl.2019.0148
• Languages: English
• ISSNs: 1750-0443

Abstract

Abstract : The present work details the synthesis of cobalt quantum‐dots (Co QDs) with size downscaling to 1–2 nm and their applications in non‐volatile memory (NVM) devices. The process of colloidal synthesis is simple and provides the control over a wide range of QDs size. The scaled‐down colloidal Co QDs are applied for the NVM device fabrication. Colloidal synthesised Co QDs are spin‐coated over silicon dioxide wafer for the fabrication of floating‐gate NVM devices. Capacitance–voltage ( C – V ) and capacitance–time ( C – t ) measurements of the fabricated NVM device indicate a low voltage operation of device. A sweep voltages as small as 1.2–4 V lead to a flat band voltage shift of 0.35–1.5 V, evidencing the low operating voltage and low power NVM applications. Further, retention characteristics show a robust retention by fabricated NVM device. In addition, C – V measurements are done for the several samples in order to study the process repeatability. The work also is compared with the other processes for the floating gate memory device.