AC‐SJ VDMOS with ultra‐low resistance. (1st April 2020)

• Record Type: Journal Article
• Authors: Wang, Yandong; Duan, Baoxing; Zhang, Chen; Wang, Xiameng; Yang, Yintang
• Is Part Of: Micro & nano letters. Volume 15:Number 4(2020)
• Page Start: 230
• Page End: 233
• Publication Date: 2020-04-01
• Subjects: power MOSFET -- semiconductor device models; conventional VDMOS -- AC‐SJ VDMOS -- carrier AC -- accumulation superjunction vertical power metal–oxide–semiconductor field‐effect transistor -- specific resistance -- breakdown voltage -- size 15.0 mum; Nanotechnology -- Periodicals; Nanostructures -- Periodicals; Microtechnology -- Periodicals; 620.5
• DOI: 10.1049/mnl.2019.0497
• Languages: English
• ISSNs: 1750-0443

Abstract

Abstract : An accumulation superjunction (AC‐SJ) vertical power metal–oxide–semiconductor field‐effect transistor (VDMOS) is proposed and its mechanism is investigated. Different from the conventional VDMOS, a number of carriers are accumulated and modulate the conductivity of the drift region when the AC‐SJ VDMOS works in the on‐state. The causes of carrier AC and the factors affecting the amount of carrier are analysed. The influences of these factors on the output characteristics are studied by simulation. Simulation results show that the on specific resistance ( R on, sp ) of the AC‐SJ VDMOS decreases from 6.64 mΩ cm 2 of the conventional VMOS to 1.53 mΩ cm 2 with the same drift region length of 15 μm. The AC‐SJ VDMOS obtains very low R on, sp by accumulating electrons while maintains high breakdown voltage due to SJ theory, thereby breaking the SJ limit in silicon.