Fabrication method for annular/shielded copper interconnects. (1st May 2017)

• Record Type: Journal Article
• Authors: Adamshick, Stephen; Burke, John; Liehr, Michael
• Is Part Of: Micro & nano letters. Volume 12:Number 5(2017)
• Page Start: 301
• Page End: 303
• Publication Date: 2017-05-01
• Subjects: copper -- silicon compounds -- tantalum compounds -- integrated circuit interconnections -- scanning electron microscopy -- electroplating -- chemical mechanical polishing -- oxidation -- diffusion; TaN -- SiN -- Cu -- diffusion‐oxidation barrier -- copper damascene processing -- tantalum nitride -- silicon nitride -- high frequency electrical measurements -- scanning electron microscopy -- shielded copper interconnects -- annular copper interconnects -- chip copper interconnects; Nanotechnology -- Periodicals; Nanostructures -- Periodicals; Microtechnology -- Periodicals; 620.5
• DOI: 10.1049/mnl.2016.0462
• Languages: English
• ISSNs: 1750-0443

Abstract

Abstract : This study outlines a method for fabricating annular/shielded on chip copper interconnects. Traditional damascene copper wires only require one diffusion barrier to prevent copper migration into dielectrics for trench style interconnects. However, for annular or shielded interconnects, an additional diffusion/oxidation barrier is required to protect the integrity of the copper especially on the trench sidewalls. Two methods are explored in this study to create the second barrier that includes materials such as tantalum nitride and silicon nitride (SiN). The experimental results are analysed using scanning electron microscopy (SEM) and high frequency electrical measurements to characterise the effectiveness of each respective technique. The results demonstrate the feasibility of creating annular/shielded copper interconnects using standard damascene processing techniques to maintain lower costs of process development. Furthermore, the results conclude the SiN based barrier effectively prevents oxidation of copper as verified with both SEM and electrical data. The development of this knowledge will aid in advancing back end interconnect technology to help solve the data bottleneck issue currently challenging the semiconductor industry.