Multi‐valued logic design methodology with double negative differential resistance transistors. (1st October 2017)

• Record Type: Journal Article
• Authors: Ji, Yuchao; Chang, Sheng; Wang, Hao; Huang, Qijun; He, Jin; Yi, Fan
• Is Part Of: Micro & nano letters. Volume 12:Number 10(2017)
• Page Start: 738
• Page End: 743
• Publication Date: 2017-10-01
• Subjects: logic gates -- negative resistance circuits -- field effect transistors -- adders; multivalued logic design methodology -- binary logic -- logic density -- circuit structure -- double negative differential resistance field effect transistor -- monostable‐multistable transition logic element -- MMLE -- MVL -- ternary logic gates -- ternary four‐input full adder -- function circuits -- binary circuit -- ternary circuit -- information load ability; Nanotechnology -- Periodicals; Nanostructures -- Periodicals; Microtechnology -- Periodicals; 620.5
• DOI: 10.1049/mnl.2017.0163
• Languages: English
• ISSNs: 1750-0443

Abstract

Abstract : Multi‐valued logic (MVL) is one of the promising alternatives of binary logic since it has a high‐logic density, which brings a vision of simpler circuit structure. Based on a novel concept as double negative differential resistance field effect transistor and its analytic description, a design methodology utilising the mechanism of monostable‐to‐multistable transition logic element (MMLE) for MVL is proposed in this study. The basic ternary logic gates are designed as a complete logic set, and a compact ternary four‐input full adder is constructed as an example of function circuits. Comparing with binary circuit and ternary circuit based on conventional design, the circuit shows advantage in device cost and other properties. The results verify that this MMLE design methodology has a good information load ability, which will have a brilliant prospect in MVL circuits.