Duty‐cycle detector based on time‐to‐digital conversion. Issue 4 (1st February 2013)

• Record Type: Journal Article
• Authors: Ravezzi, L.
• Is Part Of: Electronics letters. Volume 49:Issue 4(2013)
• Page Start: 247
• Page End: 248
• Publication Date: 2013-02-01
• Subjects: size; CMOS integrated circuits -- detector circuits -- network topology -- time‐digital conversion; duty‐cycle detector -- time‐to‐digital conversion -- analogue‐digital duty cycle corrector -- low phase input clock detection -- high phase input clock circuit detection -- digital word delivery -- input duty cycle estimation -- circuit topology -- bulk CMOS technology -- maximum linearity error -- size 28 nm; Electronics -- Periodicals; 621.381
• DOI: 10.1049/el.2012.4276
• Languages: English
• ISSNs: 0013-5194

Abstract

Abstract : A duty cycle detector based on time‐to‐digital conversion is presented. It combines the advantages of analogue (high accuracy and simplicity) and digital (digital output) duty cycle correctors in a simple and straightforward topology. Two identical circuits detect the high and low phases of the input clock and deliver two digital words. These two words are then sufficient to accurately estimate the input duty cycle. By using the same topology for both circuits, accuracy is affected only by mismatches between them. Designed in a bulk 28nm CMOS technology the proposed duty cycle detector achieves a maximum linearity error of 4% and a resolution of 0.5% over corners and an input duty cycle range of [20, 80]%.